By Bramhananda Marathe,Sandhya Nerale
The function of this publication is to supply perception and instinct into the analog and analog-mixed sign method verification. it's also a trip the writer of this ebook has been via so as to take on functional layout and verification demanding situations with country of paintings analog and combined sign designs.
Motivation for authoring this book
The electronic layout verification ability set is especially assorted than analog layout and verification. often, the analog block point verification is played through the analog designers, and electronic layout verification is played via electronic layout verification engineer. loss of pass area ability set makes it difficult to accomplish verification at mixed-signal point. for that reason, both analog clothier engineer may still study complex electronic verification suggestions or electronic layout verification engineer include analog verification to develop into analog-mixed sign verification engineer. This booklet is written preserving this new pattern in brain, for that reason it covers electronic layout basics, electronic layout verification in addition to analog layout basics, and analog functionality verification.
Organization of this book
Keeping the readers of analog verification or electronic layout verification history in brain, the ebook has first five chapters keen on the basics of the analog layout, electronic layout, and its verification. bankruptcy 6 and bankruptcy 7 specializes in the analog-mixed sign layout verification and behavioral modeling respectively. bankruptcy eight is devoted to the low energy verification innovations.
Chapter 1: advent to Analog combined sign Verification
This bankruptcy discusses in regards to the evolution of the verification methodologies, background of analog-mixed sign designs, purposes, and destiny developments.
Chapter 2: Analog layout basics
The function of this bankruptcy is to offer an outline of the analog layout basics for electronic layout historical past engineers. significant concentration is given on analog habit, layout standards and their thought instead of layout themselves, similar to voltage/current reference, a number of the easy key analog layout houses equivalent to achieve, band width, fundamentals of jitter, eye diagram, and so forth.
Chapter three: electronic layout basics
In this bankruptcy, we clarify electronic layout circulation, combinational and sequential common sense layout basics, layout for testability, thoughts of timing, and timing verification.
Chapter four: Analog Verification
This bankruptcy makes a speciality of analog functionality verification and practical verification less than the context of combined sign layout hierarchical verification instead of the aspect functionality research of the designs themselves.
Chapter five: electronic layout Verification
This bankruptcy explains the instruments and methodologies which are developed over the interval which are predicated on predictable caliber and verification potency. The bankruptcy includes the sections at the insurance pushed verification (CDV) technique, statement established verification (ABV) technique, and evaluate of the CDV utilizing Open Verification technique (OVM).
Chapter 6: Analog-Mixed sign Verification
This bankruptcy discusses in regards to the AMS verification levels, selecting the right abstraction of DUT for a given verification problem, AMS verification making plans, testplanning for AMS layout verification, and testbench improvement with re-use in brain.
Chapter 7: Analog Behavioral Modeling
This bankruptcy explains concerning the functions of analog behavioral types, modeling technique, uncomplicated examples of varied analog behavioral modeling kinds, collection of accuracy point of the versions in line with the verification plan, version verification, and signoff.
Chapter eight: Low strength Verification
The objective of this bankruptcy is to give an explanation for the low energy layout verification demanding situations, key low strength layout components, low energy layout suggestions, low energy layout and verification cycle, testplanning for low strength layout verification, strength acutely aware electronic, and AMS simulations
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Additional resources for Analog-Mixed Signal Verification
Analog-Mixed Signal Verification by Bramhananda Marathe,Sandhya Nerale